Written for an advanced-level course in digital systems design, DIGITAL SYSTEMS DESIGN USING VHDL integrates the use of the industry-standard hardware description language VHDL into the digital design process. Following a review of basic concepts of logic design in Chapter 1, the author introduces the basics of VHDL in Chapter 2, and then incorporates more coverage of VHDL topics as needed, with advanced topics covered in Chapter 8. Rather than simply teach VHDL as a programming language, this book emphasizes the practical use of VHDL in the digital design process. For example, in Chapter 9, the author develops VHDL models for a RAM memory and a microprocessor bus interface; he then uses a VHDL simulation to verify that timing specifications for the interface between the memory and microprocessor bus are satisfied. The book also covers the use of CAD tools to synthesize digital logic from a VHDL description (in Chapter 8), and stresses the use of programmable logic devices, including programmable gate arrays. Chapter 10 introduces methods for testing digital systems including boundary scan and a built-in self-test.

Features:

• Teaches the use of VHDL in the advanced digital design process; both digital design concepts and VHDL are covered simultaneously.
• Teaches the use of VHDL for modeling, simulating, and synthesizing digital systems.
• Design examples range in complexity from a simple adder to a complete microcontroller.
• Numerous examples and exercises are provided at the end of each chapter, presented at various levels of difficulty.
• Programmable gate arrays and complex PLDs are presented in Chapter 6, with complete design examples using these devices presented in later chapters.
• Includes descriptions of both Xilinx and Altera programmable logic devices.
• Now available with Aldec, Inc. ACTIVE-HDL VERSION 3.5 STUDENT EDITION. (ISBN: 0-534-37830-7)

Table of Contents:

PREFACE

1. REVIEW OF LOGIC DESIGN FUNDAMENTALS

Combinational Logic / Boolean Algebra and Algebraic Simplification / Karnaugh Maps / Designing with NAND and NOR Gates / Hazards in Combinational Networks / Flip-flops and Latches / Meanly Sequential Network Design / Design of a Moore Sequential Network / Equivalent States and Reduction of State Tables / Sequential Network Timing / Setup and Hold Times / Synchronous Design / Tristate Logic and Busses

2. INTRODUCTION TO VHDL

VHDL Description of Combinational Networks / Modeling Flip-flops using VHDL Processes / VHDL Models for a Multiplexer / Compilation and Simulation of VHDL Code / Modeling a Sequential Machine / Variables, Signals, and Constants / Arrays / VHDL Operators / VHDL Functions / VHDL Procedures / Packages and Libraries / VHDL Model for a 74163 Counter

3. DESIGNING WITH PROGRAMMABLE LOGIC DEVICES

Read-only Memories / Programmable Logic Arrays (PLAs) / Programmable Array Logic (PALs) / Other Sequential Programmable Logic Devices (PLDs) / Design of a Keypad Scanner

4. DESIGN OF NETWORKS FOR ARITHMETIC OPERATIONS

Design of a Serial Adder with Accumulator / State Graphs for Control Networks / Design of a Binary Multiplier / Multiplication of Signed Binary Numbers / Design of a Binary Divider

5. DIGITAL DESIGN WITH SM CHARTS

State Machine Charts / Derivation of SM Charts / Realization of SM Charts / Implementation of the Dice Game / Alternative Realizations for SM Charts Using Microprogramming / Linked State Machines

6. DESIGNING WITH PROGRAMMABLE GATE ARRAYS AND COMPLEX PROGRAMMABLE LOGIC DEVICES

XILINX 3000 Series FPGAs / Designing with FPGAs / XILINX 4000 Series FPGAs / Using a One-Hot State Assignment / Altera

Complex Programmable Logic Devices (CPLDs) / Altera FLEX 10K Series CPLDs

7. FLOATING-POINT ARITHMETIC

Representation of Floating-Point Numbers / Floating-Point Multiplication / Other Floating-Point Operations

8. ADDITIONAL TOPICS IN VHDL

Attributes / Transport and Inertial Delays / Operator Overloading / Multivalued Logic and Signal Resolution / IEEE-1164 Standard Logic / Generics / Generate Statements / Synthesis of VHDL Code / Synthesis Examples / Files and TEXTIO

9. VHDL MODELS FOR MEMORIES AND BUSSES

Static RAM Memory / A Simplified 486 Bus Model / Interfacing Memory to a Microprocessor Bus

10. HARDWARE TESTING AND DESIGN FOR TESTABILITY

Testing Combinational Logic / Testing Sequential Logic / Scan Testing / Boundary Scan / Built-In Self-Test

11. DESIGN EXAMPLES

UART Design / Description of the MC68HC05 Microcontroller / Design of Microcontroller CPU / Completion of the Microcontroller Design /

APPENDIX A : VHDL LANGUAGE SUMMARY

APPENDIX B : BIT PACKAGE

APPENDIX C : TEXTIO PACKAGE

APPENDIX D : BEHAVIORAL VHDL CODE FOR M6805 CPU

APPENDIX E : M6805 CPU VHDL CODE FOR SYNTHESIS

APPENDIX F : PROJECTS

REFERENCES

INDEX