Overview : FUNDAMENTALS OF LOGIC DESIGNprovides a thorough presentation of fundamental concepts for a first course in the logic design of digital systems for both engineering and computer science students. The book covers in depth such essential concepts as the use of Boolean algebra to describe the signals and interconnections in a logic network, use of systematic techniques for simplification of a logic network, interconnection of simple components to perform a more complex logic function, analysis of a sequential logic network in terms of timing charts or a state graph, and use of a control network to control the sequence of events in a digital system. It offers a balance of theory and practical applications that prepares readers for more advanced studies in digital systems design and switching theory. Ideal for use in a self-paced course, FUNDAMENTALS OF LOGIC DESIGN provides self-study aids such as reading assignments and study questions within each of its 27 study units. A computer-aided logic design program, LogicAid™, is suggested for use with this text.
Table of Contents:
PREFACE / HOW TO USE THIS BOOK FOR SELF-STUDY
1. INTRODUCTION: NUMBER SYSTEMS AND CONVERSION
Objectives / Study Guide / Digital Systems and Switching Networks / Number Systems and Conversion / Binary Arithmetic / Binary Codes / Problems
2. BOOLEAN ALGEBRA
Objectives / Study Guide / Introduction / Basic Operations / Boolean Expressions and Truth Tables / Basic Theorems / Commutative, Associative, and Distributive Laws / Simplification Problems / Multiplying out and Factoring / Problems / Laws and Theorems of Boolean Algebra
3. BOOLEAN ALGEBRA (CONTINUED)
Objectives / Study Guide / Inversion / Duality / Multiplying Out and Factoring Expressions / Exclusive - OR and Equivalence Operations / Positive and Negative Logic / Programmed Exercises and Problems
4. ALGEBRAIC SIMPLIFICATION
Objectives / Study Guide / The Consensus Theorem / Algebraic Simplification of Switching Expressions / Proving Validity of an Equation / Programmed Exercises and Problems
5. APPLICATIONS OF BOOLEAN ALGEBRA
Objectives / Study Guide / Conversion of English Sentences to Boolean Equations / Combinational Network Design Using a Truth Table / Minterm and Maxterm Expansions / Incompletely Specified Functions / Examples of Truth Table Construction / Problems
6. KARNAUGH MAPS
Objectives Study Guide / Minimum Forms of Switching Functions / 2- and 3- Variable Karnaugh Maps / 4- Variable Karnaugh Maps / Determination of Minimum Expressions Using Essential Prime Implicants / 5- and 6- Variable Karnaugh Maps / Other Uses of Karnaugh Maps / Other Forms of Karnaugh Maps / Programmed Exercises and Problems
7. QUINE-MCCLUSKEY METHOD
Objectives / Study Guide / Determination of Prime Implicants / Prime Implicant Chart / Petrick''s Method / Simplification of Incompletely Specified Functions / Simplification Using Map-Entered Variables / Conclusion / Programmed Exercises and Problems
8. MULTI-LEVEL GATE NETWORKS: NAND AND NOR GATES
Objectives / Study Guide / Multi-Level Gateway Networks / Other Types of Logic Gates / Functionally Complete Sets of Logic Gates / Design of Two-Level NAND- and NOR-Gate Networks / Design of Multi-Level NAND- and NOR-Gate Networks / Network Conversion Using Alternative Gate Symbols / Mixed Logic and Polarity Indication / Problems
9. MULTIPLE-OUTPUT NETWORKS: MULTIPLEXERS, DECODERS, READ-ONLY MEMORIES, AND PROGRAMMABLE LOGIC ARRAYS
Objectives / Study Guide / Introduction / Design of Two-Level Multiple-Output Networks / Multi-Output NAND and NOR Networks / Multiplexers / Decoders / Read-Only Memories / Programmable Logic Devices / Problems
10. COMBINATIONAL NETWORK DESIGN
Objectives / Study Guide / Review of Combinational Network Design / Design of Networks with Limited Gate Fan-in / Simulation and Testing of Logic Networks / Design Problems
11. FLIP-FLOPS
Objectives / Study Guide / Gate Delays and Timing Diagrams / The Set-Reset Flip-Flop / The Trigger Flip-Flop / The Clocked T Flip-Flop / The J-K Flip-Flop / The Clocked J-K Flip-Flop / The D Flip-Flop / Clocked Flip-Flops with Clear and Preset Inputs / Characteristic Equations / Problems and Programmed Exercises
12. COUNTERS AND SIMILAR NETWORKS
Objectives / Study Guide / Design of a Binary Counter / Counters for Other Sequences / Counter Design Using S-R Flip-Flops / Counter Design Using J-K Flip-Flops / Short-Cut Method for Deriving J-K Flip-Flop Input Equations / Counter Design Using D Flip-Flops / Design of a Code Converter / Shift Registers / Derivation of Flip-Flop Input Equations - Summary / Problems
13. ANALYSIS OF CLOCKED SEQUENTIAL NETWORKS
Objectives / Study Guide / A Sequential Parity Checker / Analysis by Signal Tracing and Timing Charts / State Tables and Graphs / General Models for Sequential Networks / Programmed Exercises and Problems 14. DERIVATION OF STATE GRAPHS AND TABLES
Objectives / Study Guide / Design of a Sequence Detector / More Complex Design Problems / Guidelines for Construction of State Graphs / Serial Data Code Conversion / Programmed Exercises and Problems
15. REDUCTION OF STATE TABLES: STATE ASSIGNMENT
Objectives / Study Guide / Elimination of Redundant States / Equivalent States / Determination of State Equivalence Using an Implication Table / Equivalent Sequential Networks / Incompletely Specified State Tables / Derivation of Flip-Flop Input Equations / Equivalent State Assignments / Guidelines for State Assignment / Problems
16. SEQUENTIAL NETWORK DESIGN
Objectives / Study Guide / Summary of Design Procedure / Design Example - Code Converter / Simulation and Testing of Sequential Networks / Overview of Computer-aided Design / Design Problems
17. ITERATIVE NETWORKS
Objectives / Study Guide / Design of a Parity Checker / Design of a Comparator / Design of a Pattern Detector / Iterative Networks with outputs from Each Cell / Problems
18. MSI INTEGRATED CIRCUITS IN SEQUENTIAL NETWORK DESIGN
Objectives / Study Guide / Integrated Circuit Shift Registers / Integrated Circuit Counters / Design of Sequential Networks Using Counters / Register Transfers and 3-State Logic / Problems
19. SEQUENTIAL NETWORK DESIGN WITH PROGRAMMABLE LOGIC DEVICES (PLDs)
Objectives / Study Guide / Design of Sequential Networks Using ROMs and PLAs / Design of Sequential Networks Using PALs / Other Sequential Programmable Logic Devices (PLDs) / Programmable Gate Arrays (PGAs) / Problems
20. NETWORKS FOR ADDITION AND SUBTRACTION
Objectives / Study Guide / Representation of Negative Numbers / Design of Binary Adders / Binary Subtracters / Problems
21. NETWORKS FOR ARITHMETIC OPERATIONS
Objectives / Study Guide / Serial Adder with Accumulator / Design of a Parallel Multiplier / Design of a Binary Divider / Programmed Exercises and Problems
22. STATE MACHINE DESIGN WITH SM CHARTS
Objectives / Study Guide / State Machine Charts / Derivation of SM Charts / Realization of SM Charts / Problems
23. ANALYSIS OF ASYNCHRONOUS SEQUENTIAL NETWORKS
Objectives / Study Guide / Introduction / Analysis of an Asynchronous Network with S-R Flip-Flops / Analysis of an Asynchronous Gate Network / Race Conditions and Cycles / Problems
24. DERIVATION AND REDUCTION OF PRIMITIVE FLOW TABLES
Objectives / Study Guide / Derivation of Primitive Flow Tables / Reduction of Primitive Flow Tables / Programmed Exercise and Problems
25. STATE ASSIGNMENT AND REALIZATION OF FLOW TABLES
Objectives / Study Guide / Introductory Example / State Assignments for 3- and 4-Row Tables / Shared-Row Assignments / Completion of the Output Table / The One-Hot Assignment / Programmed Exercise and Problems
26. HAZARDS
Objectives / Study Guide / Hazards in Combinational Networks / Detection of Static 0- and 1-Hazards / Dynamic Hazards / Design of Hazard-Free Combinational Networks / Essential Hazards / Hazard-Free Relationships Using S-R Flip-Flops / Problems
27. ASYNCHRONOUS SEQUENTIAL NETWORKS
Objectives / Study Guide / Summary of Design Procedure / Short-Cut Method for Deriving S-R Flip-Flop Input Equations / Design Example / Testing Asynchronous Sequential Networks / Design Problems /
APPENDIXES :
A : DISCRETE AND INTEGRATED CIRCUIT LOGIC GATES / Objectives / Study Guide / Diode and OR Gates / Transistor Logic Circuits / TTL Integrated Circuit Logic / MOS and CMOS Logic / Problems /
B : IEEE STANDARD LOGIC SYMBOLS / Alternative Symbols for Gates and Flip-Flops / Representation of MSI Functions /
C : PROOFS OF THEOREMS / Essential Prime Implicants / State Equivalence Theorem / Justification of Short-Cut Method for Deriving S-R Input Equations / REFERENCES / ANSWERS TO SELECTED STUDY GUIDE QUESTIONS AND PROBLEMS /
INDEX
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